About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

We are seeking an experienced Silicon Validation Engineer specializing in wafer sort testing to lead the development and execution of test programs for our large-format AI accelerator chips manufactured on TSMC's N4P process. This role is critical to ensuring first-pass silicon success by establishing robust wafer-level test methodologies, managing test coverage across large reticle-sized designs, and driving yield optimization through data-driven analysis. You will work closely with design, DFT, and production teams to define test requirements, develop test content, and establish manufacturing test flows that scale to high-volume production.

Key responsibilities

• Lead the development of comprehensive wafer sort test programs for large-format chips on advanced process nodes

• Develop test patterns for structural tests (scan, MBIST, LBIST), functional tests, and parametric measurements at wafer level

• Architect and optimize test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs

• Manage relationships with test vendors and foundry partners to ensure test program portability and manufacturability

• Drive root cause analysis of yield detractors using wafer probe data, failure analysis results, and statistical analysis techniques

• Establish test data infrastructure for real-time monitoring of wafer sort KPIs and predictive yield analytics

• Interface with production team to ensure smooth transition from engineering wafer sort to high-volume manufacturing

You may be a good fit if you have

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

• 5+ years of hands-on experience developing and deploying wafer sort test programs for advanced node semiconductors (7nm or below)

• Deep expertise with industry-standard ATE platforms (Teradyne UltraFLEX, Advantest V93000, or similar) and test program development environments

• Proven track record managing wafer sort for large die sizes

• Strong knowledge of advanced process technologies and their test requirements

• Experience with DFT methodologies including scan, ATPG, MBIST, and JTAG/boundary scan

• Proficiency in test program debugging, failure analysis correlation, and yield enhancement techniques

• Solid understanding of semiconductor manufacturing flow from wafer fab through final test

Strong candidates may also have experience with

• Leading wafer sort test development for high-performance compute, AI accelerators, or networking chips

• Advanced statistical analysis tools and yield modeling techniques (JMP, Yield Explorer, custom Python/R frameworks)

• High-speed I/O testing (SerDes, PCIe, HBM) at wafer level

• Multi-site parallel testing strategies and test time optimization for large-format dies

• Cross-functional leadership in silicon bring-up and debug activities

• Scripting and automation skills (Python, Perl, TCL) for test data analysis and reporting

• Knowledge of package-level test requirements and test hardware design

Benefits

• Full medical, dental, and vision packages, with generous premium coverage

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office

• Relocation support for those moving to San Jose (Santana Row)

How We're Different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Compensation Range: $150K - $275K