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Platform Validation Engineering Lead

Etched

Etched

San Jose, CA, USA
Posted on Sep 11, 2025

Location

San Jose

Employment Type

Full time

Location Type

On-site

Department

Platform

Platform Validation Engineer Lead

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

Etched is seeking a skilled and motivated Hardware Validation Engineer Lead to join our team. This role focuses on verifying the functionality of printed circuit boards (PCBs) and ensuring adequate margins for power and all interfaces. The engineer will play a critical lead role in collecting and analyzing data in the lab to validate hardware performance, support post-silicon characterization, and ensure robust operation across various subsystems, including PCI-E and I2C.

Representative Projects

  • PCB Function Verification: Ensure all PCB functions meet design specifications and validate critical parameters such as power and signal integrity margins.

  • Lab Data Collection: Gather and analyze data in the lab to verify margins for power delivery networks, signal integrity, and overall system robustness.

  • Post-Silicon Characterization: Collaborate on post-silicon validation efforts, identifying key performance metrics, PVT Power and thermal characterization and ensuring alignment with design targets.

  • PCI-E Margin Analysis: Evaluate PCI-E performance and ensure adequate margins for reliable operation, SI / EOM and BER.

  • Debugging & Root Cause Analysis: Identify critical bugs and drive root cause analysis to resolution, collaborating with cross-functional teams as needed.

  • DOE Experiments: Design and execute experiments (DOE) to resolve hardware issues and optimize system performance.

  • Power Validation: Validate power sequencing and ensure critical microcontroller functions are operating correctly. Power Efficiency, Noise & Transient Analysis:

  • I2C Bus Characterization: Perform in-depth characterization of I2C bus systems to ensure compliance with design specifications.

  • Issue Tracking: Maintain and track critical hardware PCB issues, documenting findings and ensuring effective communication with relevant stakeholders.

  • Collaboration: Work closely with design, firmware, and system engineering teams to ensure end-to-end hardware quality. Create a comprehensive validation plan for boards and systems.

You maybe a good fit if you have

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

  • Proven experience in hardware validation, lab testing, and PCB-level debugging.

  • Strong understanding of power and signal integrity principles, including measurement and analysis techniques.

  • Familiarity with PCI-E, I2C, and other relevant hardware interfaces and protocols.

  • Experience with lab equipment such as oscilloscopes, logic analyzers, spectrum analyzers, and power supplies.

  • Hands-on experience in debugging hardware issues and conducting root cause analysis.

  • Knowledge of power sequencing and microcontroller (uC) systems.

  • Strong analytical and problem-solving skills, scripting languages (e.g. Python, Matlab)

  • Excellent communication and teamwork abilities.


Base Salary Compensation

  • $200,000 - $250,000

Benefits

  • Full medical, dental, and vision packages, with generous premium coverage

  • Housing subsidy of $2,000/month for those living within walking distance of the office

  • Daily lunch and dinner in our office

  • Relocation support for those moving to West San Jose

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.